1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the communication of message signalled interrupts between one or more interrupt sources and a plurality of interrupt destinations.
2. Description of the Prior Art
It is known to provide communication mechanisms which support message signalled interrupts passed between one or more interrupts sources, (e.g. devices within a computer system) and a plurality of interrupt destinations (e.g. processors for processing those interrupts). It is possible that each individual interrupt destination may be formed so as to be responsive to a hundred or more different interrupts with respective interrupt numbers. The message signalled interrupt contains an address of the interrupt destination and an interrupt number at that interrupt destination. Providing such a large number of interrupt numbers allows information to be passed from the interrupt source to the interrupt destination by virtue of the interrupt number used and thereby reduce interrupt communication overhead and speed up interrupt processing.
It is also known to provide data processing systems with multiple processors where the number of processors currently active may be dynamically changed over time. When the processing workload is high, then all the processors may be active, but if the processing workload falls, then one or more of the processors may be shut down so as to save power. In this circumstance, it is necessary that a processor which is shutting down handover responsibility for any pending interrupts to be processed by that processor to a different processor. In one scenario all of the processors may shut down and transfer the responsibility for their pending interrupts onto a single remaining processor and all of the shutdown processors could have been in a state in which all of their interrupts where pending. In order to deal with this circumstance, the processor taking over responsibility must have storage resources, typically registers forming part of an interrupt handler for that processor, in sufficient number that potentially all of the interrupts from all of the other processors could be buffered.
It will be seen that the above approach does not scale well when the number of processors increases and the number of interrupts increases. The provision of registers for buffering pending interrupts associated with each processor by extending the existing storage means mechanisms leads to a requirement for an excessive overhead that undesirably increases circuit area and power consumption.